The present invention generally relates to digital signal processing systems and in particular to a digital signal processor that has a split pipeline architecture that operates on multiple data formats employing multiple memories to accomplish high speed digital signal processing functions.
The ability to perform sophisticated vector and scaler arithmetic operations in real time is a key requirement of signal processing systems. Often, however, this requirement is also accompanied by severe physical constraints upon the size, weight, power and cooling of the signal processing system. In the past, signal processor designers have had to compromise among competing requirements, many times resulting in processors with less than adequate performance.
Conventional signal processors may also be limited in performance due to relatively slow system clock rates of around five megahertz, and limited capability to operate on 16 bit fixed point data. The fixed point operational limitations of the such conventional signal processor has become significant in many application environments. Many signal processing algorithms require arithmetic computations having a large dynamic range, making 32 bit floating point processing necessary.
The ability to network modular signal processors allows a system to efficiently meet a wide range of applications. Many signal processors are limited in their capability for networking.
Conventional processor architectures may also impose hardware restrictions upon the microinstruction set employed by the system, which may result in convoluted, costly and maintenance intensive software development. Hence, such conventional signal processors do not provide flexible processing systems for many current applications.